In existing computing systems utilizing a central processing unit coupled to many different input/output (I/O) devices, such as printers, display systems, mass storage units and the like, a problem exists in coupling the central processing unit to each of the I/O devices. In the past, where the main central processing unit was used to control each of the I/O devices, it soon became overloaded and unable to function as a processor. This problem was solved by utilizing separate, generally smaller processing units, known as I/O controllers, to control the I/O devices. The I/O controller processors were controlled by the central processor to do a specific task relating to the control of the I/O device.
In the present state of the art, it is necessary that a wide variety of different processing units exist due to the inflexible and fixed design of processors and the widely varying tasks processors can perform. For example, in some I/O devices a very powerful processor is needed, while for others, a much less powerful processor is required. This fact became a serious problem for the computer system user when the user desired to upgrade a part of his system. For example, if a user desired to replace a slow printer with a much faster printer, the printer controller used with the slow printer may not be capable of handling the faster printer and the printer controller as well as the printer would have to be replaced. On the other hand, if the user replaced his central processor unit and desired to keep his existing printer, he may still have to replace his printer controller, or at least purchase a translator, since the old printer controller may not respond to the new central processor's commands.
In designing processors, whether they are for use as a main central processor, an I/O controller processor, or utilized to replace random logic functions, many problems exist due to the necessity of providing so many different types of processors for so many different uses. One solution to these problems, of course, would be to design a maximum processor and use it for all applications. This, unfortunately, becomes too great an expense burden to the products in which the maximum processor is to be used. In utilizing the different types of processors for different functions, great expense occurs in the design of these different processors. It is a complex matter to design a new processor even if it is one based on the design of another type of processor. Long periods of time and great expense are required for such simple things as determining the paths of electrical connections between the semiconductor elements of the processor. This is particularly true where the processor is the type known as a microprocessor, that is, a processor built on a single semiconductor substrate. As semiconductor technology advances, allowing more and more elements to be placed on a single semiconductor substrate, the problems of designing the conductor paths between the elements become more and more complex.
A problem adding to the cost and complexity of laying out semiconductor paths between the elements is the desire to minimize the size of the substrate. Traditionally, the art teaches that it is desirable to make the semiconductor substrate as small as possible to maximize the yields in the manufacture of semiconductive components. This, however, is in direct conflict with the desire to increase the processing power (and hence the number of elements) for microprocessors. The traditional solution to this conflict has been to add more elements on a minimized substrate and add considerable complexity to the design and layout of the conductor paths between the elements. This solution has increased both the developmental costs and the time required to develop new microprocessors.
It would be preferable to design a microprocessor with a maximum of flexibility to allow expansion or contraction as desired, even if it is at the expense of increased substrate area in order to reduce the cost and time to develop a new microprocessor. This can be done by utilizing array technology, such as program logic arrays, for the major functional units of the microprocessor. By proper arrangement of arrays on a single substrate, an entire microprocessor can be fabricated which can be expanded or contracted in size and power with little difficulty and expense in terms of cost and time.
Another problem with conventional microprocessors is that they can respond only to a single given set of instructions. An instruction set designed for one microprocessor may very well be meaningless to another type of microprocessor, especially where the second microprocessor is manufactured by a different party. This creates problems for the microprocessor user when designing new systems because old software is no longer useable if a new microprocessor is used. Also, where a new microprocessor controlled I/O controller is obtained for use with an existing central processor, the central processor may have difficulty communicating with the new I/O controller unless special interface circuits are first obtained. One of the advantages of building a microprocessor using a programmed logic array is that the array can be reprogrammed by the user to respond to a different set of instructions. This creates a very powerful tool having a wide variety of uses and eliminates many of the problems associated with changing computer equipment.
In program logic array configured microprocessors, another advantage is achieved in that clocking signals, interrupt signals and the like can be treated as data input signals to the program logic arrays. This allows a great deal of flexibility. In particular, a program logic array configured microprocessor can respond to a wide variety of different types of clocking signals or, if desired, no independent clocking signals need be used. In that situation, the provision of data to the array causes a self-clocking of the functional units to occur. Interrupt flexibility is also achieved by treating the interrupt signals as data signals, since any desired number of interrupt signals can be provided to the processor by properly programming the arrays.
In accordance with the present invention, a processor fabricated on a single semiconductor substrate includes an AND array for receiving program instructions from input sources external of the processor and for generating product signals. An OR array is provided that is interconnected to the AND array for receiving the product signals and for generating a plurality of control signals. A register array receives ones of the plurality of control signals and transfers data between the processor and data sources external of the processor. An arithmetic and logic unit array is provided which is interconnected to the register array and the OR array for executing operations on data received from the register array in accordance with ones of the plurality of control signals for generating output data. A control register array is interconnected to the OR array and the AND array for receiving ones of the plurality of control signals for controlling execution of the program instructions within the AND array.
In accordance with another aspect of the present invention, a processor is provided and includes an AND array for receiving program instructions, clock pulses and interrupt signals from input sources external of the processor and for generating product signals. The processor further includes an OR array interconnected to the AND array for receiving the product signals and for generating a plurality of control signals. A register array is provided for receiving ones of the plurality of control signals and for transferring data between the processor and data sources external of the processor. An arithmetic and logic unit array is included within the processor and is interconnected to the register array and the OR array for executing operations on data received from the register array in accordance with ones of the plurality of control signals for generating output data. The processor further includes a controller register array interconnected to the OR array and the AND array for receiving ones of the plurality of control signals for controlling execution of the program instructions within the AND array. An output register array is provided which is interconnected to receive the output data and ones of the plurality of control signals for buffering the output data between the arithmetic and logic unit array and logic circuitry external of the processor. A multiplexer register array is interconnected to the register array and to data sources external of the processor for controlling flow of data to the register array under control of ones of the plurality of control signals. Additionally, a condition code register array is provided which is interconnected to the arithmetic and logic unit array for storing condition information generated by the arithmetic and logic unit array for application to the AND array. The processor is fabricated on a single semiconductor substrate.
In accordance with yet another aspect of the present invention, a processor is fabricated on a single semiconductor substrate and includes an AND array for receiving input signals from sources external of the processor and for generating output signals along product signal lines. An OR array is provided and is disposed adjacent to the AND array on the semiconductor substrate. The OR array is interconnected to the product lines for generating control signals along control lines perpendicularly disposed to the product lines. A register array is disposed on the semiconductor substrate adjacent the OR array for receiving the control signals along register signal lines, wherein the register signal lines lie perpendicularly to the control signal lines. An arithmetic and logic unit array is disposed adjacent the register array and the AND array for receiving data from the register array along the register signal lines for generating output data.
In accordance with still another aspect of the present invention, a processor fabricated on a single semiconductor substrate for operating on data includes an AND array responsive to the application thereto of a coded input signal from sources external the substrate for providing a coded product signal having a coded state related to the code of the input signal. The product signal is provided to product signal conduction paths positioned generally along a linear path on the substrate. An OR array is positioned on the substrate to be connected with the product signal conduction paths for receiving the product signal and for generating a coded control signal on control signal conduction paths. The coded state of the control signal is related to the state of the product signal. The control signal conduction paths are positioned generally along a linear path substantially perpendicular to the product signal conduction paths. A register array is positioned on the substrate to be connected with at least a first portion of the control signal conduction paths for affecting the reception or provision of the data on data conduction paths in accordance with the state of the control signal on the first portion of the control signal conduction paths. The data conduction paths are positioned generally along a linear path substantially perpendicular to the control signal conduction paths. An output structure is positioned on the substrate to be connected with the data conduction paths and at least a second portion of the control signal conduction paths for providing data to the data conduction paths from the external sources or to the external sources from the data conduction paths in accordance with the state of the control signal on the second portion of the control signal conduction paths.